In the prior art, some processing systems have implemented more than one operating speed. In order to change operating modes, these systems have needed to stop execution by the CPU until a PLL has locked onto a desired clock signal. This has resulted in a loss of operating efficiency. Therefore, there has been a need for systems with an improved ability for transition between first and second mode of operation; and, there has been a further need for systems with an ability to sense the particular operating mode of a dynamic operating mode system.